1. Technical Field of the Invention
The present invention relates to computer processors, and in particular to switching between the processing paths of a multi-path processor.
2. Description of Related Art
Computer processors are expected to perform, at high speed, very straightforward operations such as logic or arithmetical processing operations or the shifting of data from one location to another. To improve a computer's processing speed, the most frequent developments consist in increasing the clock rates of its different component parts, and in particular the processor clock rate. The size of processors has been steadily reduced so as to be able to increase their clock speed. However, there is a limit as to how far processor size can be reduced whereas there is an ever-present demand for faster processors. Other types of developments to increase the processing speed of processors have therefore been implemented.
One known technique for improving the processing speed is to use a multi-path or multithread processor. In a processor of this kind, a task to be performed is divided into sequences of independently executable instructions, called processing paths. The processing paths thus form sub-tasks executed by one and the same central processing unit of the processor. The central processing unit switches selectively between these different paths to effect the processing. In this way, when one processing path of the processor is stopped, the central processing unit switches to another processing path.
A processor known commercially as “PowerPC” is a multi-path processor. This processor includes a number N of multiple processing paths, to which the central processing unit switches sequentially. For each processing path, the central processing unit has an associated state. A state includes, for example, a general register, a floating point register, a control register, and a link register. The states are associated with a state backup memory and restore memory. When a state has just been used for a processing path and another path is to be used at a later stage, the processed path is saved in the memory. The path to be processed at a later stage is then read in the memory and restored in the state. Transfers between the processor and the backup/restore memory are carried out by a bus. This bus is also used for the transfer of data between the processor and other external peripherals, such as a random access memory.
Such a processor and its operating process have drawbacks. Indeed, processing unit clock cycles are used to carry out state backup and load tasks, and not to process a path. Toggling between processing different paths therefore takes up processing time. The processor is furthermore complex and expensive since it uses a great number of states.
There is therefore a need for a processor or a process of implementation that resolves one or more of these drawbacks.